1. Field of Invention
The present invention relates to a power path control circuit.
2. Description of Related Art
Referring to FIG. 1, a portable electronic device usually has a battery BATT which requires to be charged from an external power supply; the power for example can be received from an adapter or an USB (through an input node). In certain applications, a system may need to operate directly under the external power when the battery is out of charge or when the battery is removed. Therefore, the circuit structure is designed as shown, in which the system can receive power from the adapter or USB, or from the battery BATT. The power path for receiving external power is controlled by a transistor power switch P0, and this switch for example can be controlled by a low drop-out regulator circuit LDO or a switch control circuit 10. The external power can be provided both to the system and the battery BATT, to charge the battery BATT when it is lack of charge. (To simplify the drawing, a control circuit for charging the battery BATT as well as other circuitry non-related to the present invention is omitted in the drawing.)
In the power path from the battery BATT to the system, a power transistor switch P1 is provided, which is controlled by a hysteresis comparator 20. When the system voltage (the voltage at the node A) is lower than the voltage at the node B, the hysteresis comparator 20 generates a low level output to turn on the PMOS transistor P1, so that the battery BATT supplies power to the system. On the other hand, when the voltage at the node A is higher than that at the node B, indicating that the system is acquiring power from the external power supply, the hysteresis comparator 20 generates a high level output to turn off the PMOS transistor P1, so that the battery BATT no more supplies power to the system.
Referring to FIG. 2, in the foregoing prior art, the system operates in three zones Z1-Z3 in terms of where it receives power from. In zone Z1, the system voltage completely comes from the adapter or the USB, since the system voltage level is higher than the battery voltage level. In zone Z3, the system voltage level is far lower than the battery voltage level, so the PMOS transistor P1 is fully turned on. However, in the transition zone Z2 between these two zones, the system voltage level is only slightly lower than the battery voltage level, causing the hysteresis comparator 20 to oscillate between on and off. More specifically, when the system voltage level is lower than the battery voltage level such that the hysteresis comparator 20 switches low, the PMOS transistor P1 is turned on. Yet, the system voltage rises up quickly at this instant because the battery BATT supplies power to the node A after the PMOS transistor P1 is turned on; hence the hysteresis comparator 20 is turned off again because the voltage difference between the node A and the node B changes. Such oscillation repeats until the system voltage reaches the zone Z3 wherein the hysteresis comparator 20 stably turns on the power switch P1.
In view of the foregoing drawbacks, it is desired to provide a power path control circuit which avoids the unstable condition mentioned above.